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PRELIMINARY
GALVANTECH, INC.
GVT7164D36 64K X 36 SYNCHRONOUS BURST SRAM
SYNCHRONOUS BURST SRAM PIPELINED OUTPUT
FEATURES
* * * * * * * * * * * * * * * * * * Fast access times: 3.5, 3.8, and 4.0ns Fast clock speed: 166, 150, 133, and 117MHz Provide high performance 3-1-1-1 access rate Fast OE# access times: 3.5ns and 3.8ns Optimal for depth expansion (one cycle chip deselect to eliminate bus contention) 3.3V -5% and +10% power supply Separate isolated output buffer supply compatible with 3.3V and 2.5V I/O (VCCQ): 2.375V to 3.6V 5V tolerant inputs except I/O's Clamp diodes to VSSQ at all inputs and outputs Common data inputs and data outputs BYTE WRITE ENABLE and GLOBAL WRITE control Three chip enables for depth expansion and address pipeline Address, data and control registers Internally self-timed WRITE CYCLE Burst control pins (interleaved or linear burst sequence) Automatic power-down for portable applications High density, high speed packages
64K x 36 SRAM
+3.3V POWER SUPPLY, FULLY REGISTERED, BURST COUNTER
GENERAL DESCRIPTION
The Galvantech Synchronous Burst SRAM family employs high-speed, low power CMOS designs using advanced triple-layer polysilicon, double-layer metal technology. Each memory cell consists of four transistors and two high valued resistors. The GVT7164D36 SRAM integrates 65,536x36 SRAM cells with advanced synchronous peripheral circuitry and a 2bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edgetriggered clock input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining chip enable (CE#), depth-expansion chip enables (CE2# and CE2), burst control inputs (ADSC#, ADSP#, and ADV#), write enables (BW1#, BW2#, BW3#, BW4#,and BWE#), and global write (GW#). Asynchronous inputs include the output enable (OE#) and burst mode control (MODE). The data outputs (Q), enabled by OE#, are also asynchronous. Addresses and chip enables are registered with either address status processor (ADSP#) or address status controller (ADSC#) input pins. Subsequent burst addresses can be internally generated as controlled by the burst advance pin (ADV#). Address, data inputs, and write controls are registered onchip to initiate self-timed WRITE cycle. WRITE cycles can be one to four bytes wide as controlled by the write control inputs. Individual byte write allows individual byte to be written. BW1# controls DQ1-DQ8 and DQP1. BW2# controls DQ9-DQ16 and DQP2. BW3# controls DQ17-DQ24and DQP3. BW4# controls DQ25-DQ32 and DQP4. BW1#, BW2# BW3#, and BW4# can be active only with BWE# being LOW. GW# being LOW causes all bytes to be written. WRITE pass-through capability allows written data available at the output for the immediately next READ cycle. This device also incorporates pipelined enable circuit for easy depth expansion without penalizing system performance. The GVT7164D36 operates from a +3.3V power supply. All inputs and outputs are TTL-compatible. The device is ideally suited for 486, PentiumTM, 680x0, and PowerPCTM systems and for systems that are benefited from a wide synchronous data bus.
OPTIONS
Timing 3.5ns access/6.0ns cycle 3.8ns access/6.7ns cycle 4.0ns access/7.5ns cycle 4.0ns access/8.5ns cycle Packages 100-pin TQFP
MARKING
-3 -4 -5 -6 T
*
Galvantech, Inc. 3080 Oakmead Village Drive, Santa Clara, CA 95051 Tel (408) 566-0688 Fax (408) 566-0699
Rev. 3/98
Pentium is a trademark of Intel Corporation. PowerPC is a trademark of IBM Corporation. Galvantech, Inc. reserves the right to change products or specifications without notice.
PRELIMINARY
GALVANTECH, INC.
FUNCTIONAL BLOCK DIAGRAM
GVT7164D36 64K X 36 SYNCHRONOUS BURST SRAM
BYTE 1 WRITE
BW1# BWE# CLK
D
Q
BYTE 2 WRITE
BW2#
D
Q
GW#
BYTE 3 WRITE
BW3#
D
Q
BYTE 4 WRITE
BW4#
D
Q
byte 4 write byte 3 write Output Buffers byte 2 write byte 1 write DQ1-DQ32, DQP1,DQP2 DQp3,DQp4
CE# CE2 CE2# OE# ZZ Power Down Logic
ENABLE
D
Q
D
Q
ADSP# A15-A2 ADSC# CLR ADV# A1-A0 MODE Binary Counter & Logic Address Register
Input Register
64K x 9 x 4 SRAM Array
OUTPUT REGISTER
D
Q
NOTE:
The Functional Block Diagram illustrates simplified device operation. See Truth Table, pin descriptions and timing diagrams for detailed information.
March 2, 1998
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Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 3/98
PRELIMINARY
GALVANTECH, INC.
GVT7164D36 64K X 36 SYNCHRONOUS BURST SRAM
PIN ASSIGNMENT (Top View)
A6 A7 CE# CE2 BW4# BW3# BW2# BW1# CE2# VCC VSS CLK GW# BWE# OE# ADSC# ADSP# ADV# A8 A9
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67
DQP3 DQ17 DQ18 VCCQ VSSQ DQ19 DQ20 DQ21 DQ22 VSSQ VCCQ DQ23 DQ24 NC VCC NC VSS DQ25 DQ26 VCCQ VSSQ DQ27 DQ28 DQ29 DQ30 VSSQ VCCQ DQ31 DQ32 DQP4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
100-pin PQFP or 100-pin TQFP
66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
DQP2 DQ16 DQ15 VCCQ VSSQ DQ14 DQ13 DQ12 DQ11 VSSQ VCCQ DQ10 DQ9 VSS NC VCC ZZ DQ8 DQ7 VCCQ VSSQ DQ6 DQ5 DQ4 DQ3 VSSQ VCCQ DQ2 DQ1 DQP1
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
PIN DESCRIPTIONS
QFP PINS
37, 36, 35, 34, 33, 32, 100, 99, 82, 81, 44, 45, 46, 47, 48, 49 93,94,95,96
SYMBOL
A0-A15
TYPE
InputSynchronous
BW1#, BW2#, BW3#, BW4# BWE# GW#
InputSynchronous
87 88
InputSynchronous
InputSynchronous
89
CLK
InputSynchronous
98 92
CE# CE2#
InputSynchronous
InputSynchronous
March 2, 1998
Rev. 3/98
MODE A5 A4 A3 A2 A1 A0 NC NC VSS VCC NC NC A10 A11 A12 A13 A14 A15 NC
DESCRIPTION
Addresses: These inputs are registered and must meet the setup and hold times around the rising edge of CLK. The burst counter generates internal addresses associated with A0 and A1, during burst cycle and wait cycle. Byte Write: A byte write is LOW for a WRITE cycle and HIGH for a READ cycle. BW1# controls DQ1-DQ8 and DQP1. BW2# controls DQ9-DQ16 and DQP2. BW3# controls DQ17-DQ24 and DQP3. BW4# controls DQ25-DQ32 and DQP4. Data I/O are high impedance if either of these inputs are LOW, conditioned by BWE# being LOW. Write Enable: This active LOW input gates byte write operations and must meet the setup and hold times around the rising edge of CLK. Global Write: This active LOW input allows a full 36-bit WRITE to occur independent of the BWE# and BWn# lines and must meet the setup and hold times around the rising edge of CLK. Clock: This signal registers the addresses, data, chip enables, write control and burst control inputs on its rising edge. All synchronous inputs must meet setup and hold times around the clock's rising edge. Chip Enable: This active LOW input is used to enable the device and to gate ADSP#. Chip Enable: This active LOW input is used to enable the device.
3
Galvantech, Inc. reserves the right to change products or specifications without notice.
PRELIMINARY
GALVANTECH, INC.
PIN DESCRIPTIONS (continued)
QFP PINS
97 86 83 84
GVT7164D36 64K X 36 SYNCHRONOUS BURST SRAM
SYMBOL
CE2 OE# ADV# ADSP#
TYPE
inputSynchronous
DESCRIPTION
Chip enable: This active HIGH input is used to enable the device. Output Enable: This active LOW asynchronous input enables the data output drivers. Address Advance: This active LOW input is used to control the internal burst counter. A HIGH on this pin generates wait cycle (no address advance). Address Status Processor: This active LOW input, along with CE# being LOW, causes a new external address to be registered and a READ cycle is initiated using the new address. Address Status Controller: This active LOW input causes device to be de-selected or selected along with new external address to be registered. A READ or WRITE cycle is initiated depending upon write control inputs. Mode: This input selects the burst sequence. A LOW on this pin selects LINEAR BURST. A NC or HIGH on this pin selects INTERLEAVED BURST. Snooze: This active HIGH input puts the device in low power consumption standby Data Inputs/Outputs: First Byte is DQ1-DQ8. Second Byte is DQ9-DQ16. Third Byte is DQ17-DQ24. Fourth Byte is DQ25-DQ32. Input data must meet setup and hold times around the rising edge of CLK. Parity Inputs/Outputs: DQP1 is parity bit for DQ1-DQ8 and DQP2 is parity bit for DQ9DQ16. DQP3 is parity bit for DQ17-DQ24 and DQP4 is parity bit for DQ25-DQ32. Core power Supply: +3.3V -5% and +10% Ground: GND. Output Buffer Supply: +2.375 to 3.6V Output Buffer Ground: GND No Connect: These signals are not internally connected.
Input InputSynchronous
InputSynchronous
85
ADSC#
InputSynchronous
31 64 52, 53, 56, 57, 58, 59, 62, 63, 68, 69, 72-75, 78, 79, 2, 3, 6-9, 12, 13, 18, 19, 22-25, 28, 29 51, 80, 1, 30 15, 41,65, 91 17, 40, 67, 90 4, 11, 20, 27, 54, 61, 70, 77 5, 10, 21, 26, 55, 60, 71, 76 14, 16, 38, 39, 42, 43,50, 66
MODE ZZ DQ1-DQ32
InputStatic InputInput/ Output
Asynchronous mode. For normal operation, this input has to be either LOW or NC (No Connect).
DQP1, DQP2, DQP3, DQP4 VCC VSS VCCQ VSSQ NC
Input/ Output Supply Ground I/O Supply I/O Ground -
BURST ADDRESS TABLE (MODE = NC/VCC)
First Address (external)
A...A00 A...A01 A...A10 A...A11
Second Address (internal)
A...A01 A...A00 A...A11 A...A10
Third Address (internal)
A...A10 A...A11 A...A00 A...A01
Fourth Address (internal)
A...A11 A...A10 A...A01 A...A00
BURST ADDRESS TABLE (MODE = GND)
First Address (external)
A...A00 A...A01 A...A10 A...A11
Second Address (internal)
A...A01 A...A10 A...A11 A...A00
Third Address (internal)
A...A10 A...A11 A...A00 A...A01
Fourth Address (internal)
A...A11 A...A00 A...A01 A...A10
March 2, 1998
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Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 3/98
PRELIMINARY
GALVANTECH, INC.
TRUTH TABLE
OPERATION ADDRESS USED CE# CE2#
GVT7164D36 64K X 36 SYNCHRONOUS BURST SRAM
CE2
ADSP# ADSC#
ADV#
WRITE#
OE#
CLK
DQ
Deselected Cycle, Power Down Deselected Cycle, Power Down Deselected Cycle, Power Down Deselected Cycle, Power Down Deselected Cycle, Power Down READ Cycle, Begin Burst READ Cycle, Begin Burst WRITE Cycle, Begin Burst READ Cycle, Begin Burst READ Cycle, Begin Burst READ Cycle, Continue Burst READ Cycle, Continue Burst READ Cycle, Continue Burst READ Cycle, Continue Burst WRITE Cycle, Continue Burst WRITE Cycle, Continue Burst READ Cycle, Suspend Burst READ Cycle, Suspend Burst READ Cycle, Suspend Burst READ Cycle, Suspend Burst WRITE Cycle, Suspend Burst WRITE Cycle, Suspend Burst
None None None None None External External External External External Next Next Next Next Next Next Current Current Current Current Current Current
H L L L L L L L L L X X H H X H X X H H X H
X X H X H L L L L L X X X X X X X X X X X X
X L X L X H H H H H X X X X X X X X X X X X
X L L H H L L H H H H H X X H X H H X X H X
L X X L L X X L L L H H H H H H H H H H H H
X X X X X X X X X X L L L L L L H H H H H H
X X X X X X X L H H H H H H L L H H H H L L
X X X X X L H X L H L H L H X X L H L H X X
L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H
High-Z High-Z High-Z High-Z High-Z Q High-Z D Q High-Z Q High-Z Q High-Z D D Q High-Z Q High-Z D D
Note:
1.
2. 3. 4. 5. 6. 7.
X means "don't care." H means logic HIGH. L means logic LOW. WRITE# = L means [BWE# + BW1#*BW2#*BW3#*BW4#]*GW# equals LOW. WRITE# = H means [BWE# + BW1#*BW2#*BW3#*BW4#]*GW# equals HIGH. BW1# enables write to DQ1-DQ8 and DQP1. BW2# enables write to DQ9-DQ16 and DQP2. BW3# enables write to DQ17DQ24 and DQP3. BW4# enables write to DQ25-DQ32 and DQP4. All inputs except OE# must meet setup and hold times around the rising edge (LOW to HIGH) of CLK. Suspending burst generates wait cycle. For a write operation following a read operation, OE# must be HIGH before the input data required setup time plus High-Z time for OE# and staying HIGH throughout the input data hold time. This device contains circuitry that will ensure the outputs will be in High-Z during power-up. ADSP# LOW along with chip being selected always initiates an READ cycle at the L-H edge of CLK. A WRITE cycle can be performed by setting WRITE# LOW for the CLK L-H edge of the subsequent wait cycle. Refer to WRITE timing diagram for clarification.
PARTIAL TRUTH TABLE FOR READ/WRITE
FUNCTION READ READ WRITE one byte WRITE all bytes WRITE all bytes GW# H H H H L BWE# H L L L X BW1# X H L L X BW2# X H H L X BW3# X H H L X BW4# X H H L X
March 2, 1998
5
Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 3/98
PRELIMINARY
GALVANTECH, INC.
ABSOLUTE MAXIMUM RATINGS*
GVT7164D36 64K X 36 SYNCHRONOUS BURST SRAM
*Stresses greater than those listed uunder "Absolute Maximum Ratings" may cause permanent damage to the device.This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Voltage on VCC Supply Relative to VSS........-0.5V to +4.6V VIN .....................................................................-0.5V to +6V Storage Temperature (plastic) .......................-55oC to +150o Junction Temperature ....................................................+150o Power Dissipation ...........................................................1.6W Short Circuit Output Current ......................................100mA
DC ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS
(0oC Ta
70C; VCC = 3.3V -5% and +10% unless otherwise noted)
CONDITIONS SYMBOL
VIH VIl 0V < VIN < VCC Output(s) disabled, 0V < VOUT < VCC IOH = -4.0mA IOL = 8.0mA ILI ILO VOH VOL VCC VCCQ 3.135 2.375
DESCRIPTION
Input High (Logic 1) voltage Input Low (Logic 0) Voltage Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage Supply Voltage I/O Supply
MIN
2.0 -0.3 -2 -2 2.4
MAX
VCC+0.3 0.8 2 2 0.4 3.6 3.6
UNITS
V V uA uA V V V
NOTES
1,2 1, 2 14 1, 11 1, 11 1
DESCRIPTION
Power Supply Current: Operating CMOS Standby
CONDITIONS
Device selected; all inputs < VILor > VIH;cycle time > tKC MIN; VCC =MAX; outputs open Device deselected; VCC = MAX; all inputs < VSS +0.2 or >VCC -0.2; all inputs static; CLK frequency = 0 Device deselected; all inputs < VIL or > VIH ; all inputs static; VCC = MAX; CLK frequency = 0 Device deselected; all inputs < VIL or > VIH; VCC = MAX; CLK cycle time > tKC MIN
SYM
Icc
TYP
300
-3
425
-4
400
-5
375
-6
350
UNITS NOTES
mA 3, 12, 13
ISB2
1
2
2
2
2
mA
12,13
TTL Standby
ISB3
4
10
10
10
10
mA
12,13
Clock Running
ISB4
80
130
130
130
130
mA
12,13
March 2, 1998
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Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 3/98
PRELIMINARY
GALVANTECH, INC.
AC ELECTRICAL CHARACTERISTICS
(Note 5) (0oC
GVT7164D36 64K X 36 SYNCHRONOUS BURST SRAM
TA 70oC; VCC = 3.3V -5% and +10%)
-3 166MHz
SYM MIN MAX
DESCRIPTION
Clock Clock cycle time Clock HIGH time Clock LOW time Output Times Clock to output valid Clock to output invalid Clock to output in Low-Z Clock to output in High-Z OE to output valid OE to output in Low-Z OE to output in High-Z Setup Times Address, Controls and Data In Hold Times Address, Controls and Data In
t t t t t t t t
-4 150MHz
MIN MAX
-5 133MHz
MIN MAX
-6 117MHz
MIN MAX UNITS NOTES
KC KH KL
6.0 2.4 2.4 3.5 1.5 0 1.5 0 3.5 1.5 0.5 6.0 3.5
6.7 2.6 2.6 3.8 1.5 0 1.5 0 3.5 1.5 0.5 6.7 3.5
7.5 2.8 2.8 4.0 1.5 0 1.5 0 3.8 1.5 0.5 7.5 3.8
8.5 3.4 3.4 4.0 1.5 0 1.5 0 3.8 2.0 0.5 8.5 3.8
ns ns ns ns ns ns ns ns ns ns ns ns 4, 6,7 4, 6,7 9 4, 6,7 4, 6,7 10 10
t
t
KQ
KQX
KQLZ OEQ
KQHZ
t
t
OELZ
OEHZ S
H
CAPACITANCE
DESCRIPTION
Input Capacitance Input/Output Capacitance (DQ)
CONDITIONS
TA = 25oC; f = 1 MHz VCC = 3.3V
SYMBOL
CI CO
TYP
4 7
MAX
5 8
UNITS
pF pF
NOTES
4 4
THERMAL CONSIDERATION
DESCRIPTION
Thermal Resistance - Junction to Ambient Thermal Resistance - Junction to Case
CONDITIONS
Still air, soldered on 4.25 x 1.125 inch 4-layer PCB
SYMBOL
JA JC
TQFP TYP
25 9
UNITS
o o
NOTES
C/W C/W
TYPICAL OUTPUT BUFFER CHARACTERISTICS
OUTPUT HIGH VOLTAGE
VOH (V) -0.5 0 0.8 1.25 1.5 2.3 2.7 2.9 3.4
PULL-UP CURRENT
(m) in (m) ax -38 -38 -38 -26 -20 0 0 0 0 -105 -105 -105 -83 -70 -30 -10 0 0
OUTPUT LOW VOLTAGE
VOL (V) -0.5 0 0.4 0.8 1.25 1.6 2.8 3.2 3.4
PULL-DOWN CURRENT
L(m) in L(m) ax 0 0 10 20 31 40 40 40 40 0 0 20 40 63 80 80 80 80
March 2, 1998
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Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 3/98
PRELIMINARY
GALVANTECH, INC.
AC TEST CONDITIONS Input pulse levels Input rise and fall times Input timing reference levels Output reference levels Output load 0V to 3.0V 1.5ns 1.5V 1.5V See Figures 1
GVT7164D36 64K X 36 SYNCHRONOUS BURST SRAM
OUTPUT LOADS
DQ Z0 = 50 50 Vt = 1.5V Fig. 1 OUTPUT LOAD EQUIVALENT 3.3v 317 DQ 351 5 pF
Fig. 2 OUTPUT LOAD EQUIVALENT
NOTES
1. 2. 3. 4. 5. 6. 7. 8. All voltages referenced to VSS (GND). Overshoot: Undershoot: VIH +6.0V for t tKC /2. VIL -2.0V for t tKC /2
15. Capacitance derating applies to capacitance different from the load capacitance shown in Fig. 1.
Icc is given with no output current. Icc increases with greater output loading and faster cycle times. This parameter is sampled. Test conditions as specified with the output loading as shown in Fig. 1 unless otherwise noted. Output loading is specified with CL=5pF as in Fig. 2. At any given temperature and voltage condition, tKQHZ is less than tKQLZ and tOEHZ is less than tOELZ. A READ cycle is defined by byte write enables all HIGH or ADSP# LOW along with chip enables being active for the required setup and hold times. A WRITE cycle is defined by at one byte or all byte WRITE per READ/WRITE TRUTH TABLE. OE# is a "don't care" when a byte write enable is sampled LOW.
9.
10. This is a synchronous device. All synchronous inputs must meet specified setup and hold time, except for "don't care" as defined in the truth table. 11. AC I/O curves are available upon request. 12. "Device Deselected" means the device is in POWER -DOWN mode as defined in the truth table. "Device Selected" means the device is active. 13. Typical values are measured at 3.3V, 25oC and 8.5ns cycle time. 14. MODE pin has an internal pull-up and ZZ pin has an internal pull-down. These two pins exhibit an input leakage current of +30 A.
March 2, 1998
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Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 3/98
PRELIMINARY
GALVANTECH, INC.
GVT7164D36 64K X 36 SYNCHRONOUS BURST SRAM
READ TIMING
tKC tKL
CLK
tS tKH
ADSP#
tH
ADSC#
tS
ADDRESS BW1#, BW2#, BW3#, BW4#, BWE#, GW# CE# (See Note)
A1
tH
A2
tS
ADV#
tH
OE#
tKQ tKQLZ tOELZ tOEQ tKQ
DQ
Q(A1)
Q(A2)
Q(A2+1)
Q(A2+2)
Q(A2+3)
Q(A2)
Q(A2+1)
SINGLE READ
BURST READ
Note: CE# active in this timing diagram means that all chip enables CE#, CE2, and CE2# are active.
March 2, 1998
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Rev. 3/98
PRELIMINARY
GALVANTECH, INC.
GVT7164D36 64K X 36 SYNCHRONOUS BURST SRAM
WRITE TIMING
CLK
tS
ADSP#
tH
ADSC#
tS
ADDRESS BW1#, BW2#, BW3#, BW4#, BWE# GW# CE# (See Note)
A1
tH
A2
A3
tS
ADV#
tH
OE#
tOEHZ tKQX
DQ
Q
D(A1)
D(A2)
D(A2+1)
D(A2+1)
D(A2+2)
D(A2+3)
D(A3)
D(A3+1)
D(A3+2)
SINGLE WRITE
BURST WRITE
BURST WRITE
Note: CE# active in this timing diagram means that all chip enables CE#, CE2, and CE2# are active.
March 2, 1998
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Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 3/98
PRELIMINARY
GALVANTECH, INC.
GVT7164D36 64K X 36 SYNCHRONOUS BURST SRAM
READ/WRITE TIMING
CLK
tS
ADSP#
tH
ADSC#
tS
ADDRESS BW1#, BW2#, BW3#, BW4#, BWE#, GW# CE# (See Note) ADV#
A1
A2
tH
A3
A4
A5
OE#
DQ
Q(A1) Single Reads
Q(A2)
D(A3) Single Write
Q(A3) Pass Through
Q(A4)
Q(A4+1) Burst Read
Q(A4+2)
D(A5)
D(A5+1)
Burst Write
Note: CE# active in this timing diagram means that all chip enables CE#, CE2, and CE2# are active.
March 2, 1998
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Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 3/98
PRELIMINARY
GALVANTECH, INC.
100 Pin TQFP Package Dimensions
GVT7164D36 64K X 36 SYNCHRONOUS BURST SRAM
16.00 + 0.10 14.00 + 0.10
#1
20.00 + 0.10
22.00 + 0.10
1.40 + 0.05
1.60 Max Note: All dimensions in Millimeters
0.65 Basic
0.30 + 0.08
0.60 + 0.15
March 2, 1998
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Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 3/98
PRELIMINARY
GALVANTECH, INC.
Ordering Information
GVT7164D36 64K X 36 SYNCHRONOUS BURST SRAM
GVT 7164D36 X - X
Galvantech Prefix Part Number Speed (3 = 3.5ns access/6.0ns cycle 4 = 3.8ns access/6.7ns cycle 5 = 4.0ns access/7.5ns cycle 6 = 4.0ns access/8.5ns cycle) Package (T = 100 PIN TQFP)
March 2, 1998
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Rev. 3/98

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